The present invention relates to the formation of metal interconnection layers during the manufacture of semiconductor devices, and more particularly to the formation of a damascene structure in a metal interconnect region by a via fill dual damascene technique.
The escalating requirements for high-density and performance associated with ultra large-scale integration semiconductor wiring require responsive changes in interconnection technology. Such escalating requirements have been found difficult to satisfy in terms of providing a low RC (resistance capacitance) interconnection pattern, particularly where sub-micron via contacts and trenches have high aspect ratios imposed by miniaturization.
Conventional semiconductor devices typically comprise a semiconductor substrate, normally of doped monocrystalline silicon, and a plurality of sequentially formed dielectric layers and conductive patterns. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by inter-wiring spacings. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via hole, while a conductive plug filling a contact hole establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor chips comprising five or more levels of metalization are becoming more prevalent as device geometries shrink to sub-micron levels.
A conductive plug filling a via hole is typically formed by depositing a dielectric interlayer on a conductive layer comprising at least one conductive pattern, forming an opening in the dielectric layer by conventional photolithographic and etching techniques, and filling the opening with a conductive material, such as tungsten (W). Excess conductive material on the surface of the dielectric layer is typically removed by chemical mechanical polishing (CMP). One such method is known as damascene and basically involves forming an opening in the dielectric interlayer and filling the opening with a metal. Dual damascene techniques involve forming an opening comprising a lower contact or via hole section in communication with an upper trench section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug and electrical contact with a conductive line.
High-performance microprocessor applications require rapid speed of semiconductor circuitry. The control speed of semiconductor circuitry varies inversely with the resistance and capacitance of the interconnect pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Miniaturization demands long interconnects having small contacts and small cross-sections. Thus, the interconnection pattern limits the speed of the integrated circuit. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more as in sub-micron technologies, the interconnection capacitance limits the circuit node capacitance loading, and hence, the circuit speed. As integration density increases and feature size decreases in accordance with sub-micron design rules, e.g., a design rule of about 0.1 micron and below, the rejection rate due to integrated circuit speed delays severely limits production throughput and significantly increases manufacturing costs.
In prior technologies, aluminum was used in very large scale integration interconnect metalization. Copper and copper alloys have received considerable attention as a candidate for replacing aluminum in these metalizations. Copper has a lower resistivity than aluminum and improved electrical properties compared to tungsten, making copper a desirable metal for use as a conductive plug as well as conductive wiring.
In the formation of a dual damascene structure in a self-aligned manner, a conductive line and vias that connect the line to conductive elements in a previously formed underlying conductive layer, are simultaneously deposited. A conductive material is deposited into openings (e.g., the via holes and trenches) created in dielectric material that overlays the conductive interconnect layer. Typically, a first layer of dielectric material is deposited over a bottom etch stop layer that covers and protects the conductive interconnect layer. A middle etch stop layer is then deposited over the first dielectric layer. A pattern is then etched into the middle etch stop layer to define the feature, such as a via hole, that will later be etched into the first dielectric layer. Once the middle etch stop layer is patterned, a second dielectric layer is deposited on the middle etch stop layer. The hard mask layer may then be deposited on the second dielectric layer. A desired feature, such as a trench, is etched through the hard mask layer and the second dielectric layer. This etching continues so that the first dielectric layer is etched in the same step as the second dielectric layer. The etching of the two dielectric layers in a single etching step reduces the number of manufacturing steps. The bottom etch stop layer within the via hole, which has protected the conductive material in the conductive interconnect layer, is then removed with a different etchant chemistry. With the via holes now formed in the first dielectric layer and a trench formed in the second dielectric layer, conductive material is simultaneously deposited in the via and the trench in a single deposition step. (If copper is used as the conductive material, a barrier layer is conventionally deposited first to prevent copper diffusion.) The conductive material makes electrically conductive contact with the conductive material in the underlying conductive interconnect layer.
In efforts to improve the operating performance of a chip, low k dielectric materials have been increasingly investigated for use as replacements for dielectric materials with higher k values. Lowering the overall k values of the dielectric layers employed in the metal interconnect layers lowers the RC of the chip and improves its performance. However, low k materials, such as benzocyclobutene (BCB), hydrogen silsesquioxane (HSQ), SiOF, etc., are often more difficult to handle than traditionally employed higher k materials, such as an oxide. For example, inorganic low k dielectric materials are readily damaged by techniques used to remove photoresist materials after the patterning of a layer. Hence, a feature formed in an inorganic low k dielectric layer may be damaged when the photoresist layer used to form the trench is removed. This is of special concern in a dual damascene arrangement if formed in a conventional manner since the inorganic material in the lower, via layer, will be damaged two times. In other words, the inorganic dielectric material in the via layer will be damaged a first time by the removal of photoresist used in forming the via. The same inorganic low k dielectric material in the via layer will also be damaged a second time when the upper layer, the trench layer, is patterned and the photoresist is removed.
An area of concern in the formation of trench and via interconnect structures by dual damascene technique is the possibility of misalignment of the via and the trench. As seen in the top view of FIG. 17, a via 70 that has been formed in a lower dielectric layer is misaligned with respect to the trench (and the subsequently formed conductive line 60). Hence, only a portion of the via 70 is filled with conductive material to form the conductive plug 62.
A side view of the structure of FIG. 17 is depicted in FIG. 16. The pattern 68 formed in the middle etch stop layer 65 over the first dielectric layer 64 is misaligned with respect to the trench pattern. When the trench in the second dielectric layer 66 and the via are etched in a simultaneous anisotropic etch, the etch will proceed in accordance with the overlying trench pattern. This causes only a portion of the intended via to be opened, since the via is not fully underneath the trench. Upon subsequent filling with conductive material, the conductive plug 62 that is formed is narrower than intended. This undesirably increases the resistance of the conductive plug 62, leading to increases in RC.
There is a need for a method and arrangement for providing an interconnect structure which allows an inorganic low k dielectric layer to be employed in a via layer without subjecting the via to two separate damaging process steps. There is also a need to assure that fall width of a via is provided directly underneath a conductive line formed in a trench so that the conductive plug in the via has its full intended width.
These and other needs are met by embodiments of the present invention which provide a method of forming an interconnect structure comprising the steps of depositing a first dielectric material over a conductive layer to form a first dielectric layer. The first dielectric material is an inorganic dielectric material. An etch stop layer is formed on the first dielectric layer. The etch stop layer and the first dielectric layer are etched to form a slot via in the first dielectric layer. The slot via extends with a slot length in a first direction within the first dielectric layer. A second dielectric material is then deposited in the slot via and over the etch stop layer to form a second dielectric layer over the refilled slot via and the etch stop layer. The second dielectric material is an organic low k dielectric material. The refilled slot via is etched simultaneously with the second dielectric layer so that a feature is formed that extends within the second dielectric layer in a second direction that is normal to the first direction. At least a portion of the slot via is etched. The feature in the second dielectric layer has a width in the second direction that is less than the slot length, with the entire width of the feature being over the slot via.
The provision in a first dielectric layer of a slot via that is wider than the width of the trench assures that the conductive plug that is formed will be as wide as the overlying conductive line. Also, by depositing a second dielectric material within the via, after the initial formation of the via, the second etching of a via is through newly deposited dielectric material. This has the advantage of reducing the amount of damage sustained in the via formed in the inorganic dielectric material in the first dielectric layer by a resist removal process. This has the effect of increasing structural integrity of the inorganic dielectric layer and the formation of the conductive plug in the first dielectric layer.
The earlier stated needs are met by another embodiment of the present invention which provides a method of forming an interconnect structure comprising forming a slot via in a first dielectric layer, the slot via having a width and a length extending in a first direction in the plane of the first dielectric layer. A second dielectric layer is deposited on the first dielectric layer and in the slot via to refill the via. The dielectric material in the first dielectric layer is inorganic dielectric material and in the second dielectric layer is an organic dielectric material. The second dielectric layer and the refilled via are simultaneously etched to form a trench in the second dielectric layer, and a via in the first dielectric layer. The trench has a width and a length extending in a second direction in the plane of the second dielectric layer. The first and second directions are substantially normal to one another. The width of the trench is less than the length of the slot via. The etched via has a width substantially equal to the width of the line and is substantially entirely under the line. The via and the trench are then filled with conductive material.
The earlier stated needs are also met by another embodiment of the present invention which provides an interconnect structure comprising a first dielectric layer comprising an inorganic dielectric material. The interconnect structure also has an etch stop layer with patterned slot extending in a first direction. A second dielectric layer is over the etch stop layer. The second dielectric layer comprises an organic dielectric material, with some of the organic dielectric material being in the first dielectric layer within a slot via region defined by the patterned slot. A conductive stud is provided within a via formed in the slot via region of the first dielectric layer. A conductive line is formed in the second dielectric layer and extends in a second direction normal to the first direction. The conductive line and the conductive stud have substantially the same width. Substantially the entire width of the conductive stud is located directly beneath the conductive line.
The foregoing and other features, aspects, and advantages of the present invention will become more apparent in the following detail description of the present invention when taken in conjunction with the accompanying drawings.